return 0;
}
+static void print_PCT(struct xen_pct_register *ptr)
+{
+ printk(KERN_INFO "\t_PCT: descriptor=%d, length=%d, space_id=%d, "
+ "bit_width=%d, bit_offset=%d, reserved=%d, address=%"PRId64"\n",
+ ptr->descriptor, ptr->length, ptr->space_id, ptr->bit_width,
+ ptr->bit_offset, ptr->reserved, ptr->address);
+}
+
static void print_PSS(struct xen_processor_px *ptr, int count)
{
int i;
- printk(KERN_INFO "\t_PSS:\n");
+ printk(KERN_INFO "\t_PSS: state_count=%d\n", count);
for (i=0; i<count; i++){
printk(KERN_INFO "\tState%d: %"PRId64"MHz %"PRId64"mW %"PRId64"us "
"%"PRId64"us 0x%"PRIx64" 0x%"PRIx64"\n",
ptr->num_processors);
}
+static void print_PPC(unsigned int platform_limit)
+{
+ printk(KERN_INFO "\t_PPC: %d\n", platform_limit);
+}
+
int set_px_pminfo(uint32_t acpi_id, struct xen_processor_performance *dom0_px_info)
{
int ret=0, cpuid;
memcpy ((void *)&pxpt->status_register,
(void *)&dom0_px_info->status_register,
sizeof(struct xen_pct_register));
+ print_PCT(&pxpt->control_register);
+ print_PCT(&pxpt->status_register);
}
if ( dom0_px_info->flags & XEN_PX_PSS )
{
if ( dom0_px_info->flags & XEN_PX_PPC )
{
pxpt->platform_limit = dom0_px_info->platform_limit;
+ print_PPC(pxpt->platform_limit);
if ( pxpt->init == XEN_PX_INIT )
{